1. Field of the Invention
The present invention relates to a test pattern generating apparatus for automatically generating the test pattern of a digital circuit, and particularly for a synchronized sequential circuit.
2. Description of the Prior Art
As the degree of integration of large scale Integrated (LSI) devices has increased, there has been a direct and sharp drop in the observability of internal LSI device operation. The automatic test pattern generation of used to detect faulty device has therefore become an extremely important and difficult problem. As a result, semiconductor devices constructed so that the logical values of all circuit elements are observable have become a key component of current faulty LSI device detecting technologies. A typical example of this technology is the cross check technology described by C. Writz, et al., in the paper "Cross Check: An ASIC Testability Solution" presented in the spring 1990 issue of the COMPCON technical digest (pp. 444-448).
Semiconductor testing under these observable conditions applies a test pattern capable of setting the logical value of each signal line in the circuit to 1 (ON) and 0 (OFF) while measuring the logical value of each line. Specifically, if a logical value that differs from the logical value returned by fault-free circuit is detected, the tested device As determined to have a fault. The key to this technology, therefore, is the ability to develop a test pattern generating apparatus that can obtain a test pattern capable of setting each signal line to 1 and 0 with a high detection rate and at high speed.
The literature contains many different proposals for the test pattern generating methods used in these conventional test pattern generating apparatuses. One typical example is the path sensitization method known as PODEM. This method assumes (sets) a fault on an internal signal line. To detect the fault, the logical values on the path up to the faulty signal line are set in reverse order to the input side while searching for the suitable input test pattern. However, a contradiction-free input test pattern will not necessarily always be found when searching by setting the logical values in reverse order, and it becomes necessary to perform another search by setting a different logical value. This is known as "backtracking," and because backtracking is required, the calculations performed and the amount of memory required for the path sensitization method both increase.
One test pattern generating apparatus with no backtracking is described in Japanese patent laid-open number H3-134579. The application of a test pattern generating method in a conventional test pattern generating apparatus is described briefly below with reference to FIGS. 10, 11, and 12.
FIG. 10 is a flow chart of the operation of the input search method of the conventional test pattern generating apparatus, and FIGS. 11 and 12 are graphs showing the result of the analog conversion function of the AND and OR devices, respectively. The conventional test pattern generating apparatus approximates the digital logic with the analog functions shown in FIGS. 11 and 12, and defines the cost of differences in the analog logic values of a fault-free and a faulty circuit. The test pattern generating process first assumes one fault, and then searches for the input optimizing the cost according to the flow chart in FIG. 10. The input search method selects one test vector, calculates the cost of the vector for which the Hamming distance (or signal distance) adjoins the test vector, and assigns the optimized cost vector as the next test vector. This search loop is repeated until the input that can detect the fault is determined. Thus, this conventional test pattern generating apparatus performs this process for all faults to generate the test pattern for a given semiconductor circuit.
However, specifically because this conventional test pattern generating apparatus assumes one fault and generates a corresponding test pattern, and repeats this process for all faults, the computation time required to generate all test pattern for all faults increases, and the resulting test pattern becomes longer.